A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm

Vincent Migliore (1, 2) , Cédric Seguin (2, 1) , Maria Méndez Real (2, 1) , Vianney Lapotre (2, 1) , Arnaud Tisserand (3, 1) , Caroline Fontaine (4, 5) , Guy Gogniat (2, 1) , Russell Tessier (6)

1 Lab-STICC_UBS_CACS_MOCS
2 UBS - Université de Bretagne Sud
3 CNRS - Centre National de la Recherche Scientifique
4 Lab-STICC_TB_CID_SFIIS
5 IMT Atlantique - ITI - Département lmage et Traitement Information
6 UMass Amherst - University of Massachusetts [Amherst]

Somewhat Homomorphic Encryption (SHE) schemes can be used to carry out operations on ciphered data. In a cloud computing scenario, personal information can be processed secretly, inferring a high level of confidentiality. The principle limitation of SHE is the size of ciphertext compared to the size of the message. This issue can be addressed by using a batching technique that "packs" several messages into one ciphertext. However, this method leads to important drawbacks in standard implementations. This paper presents a fast hardware/software co-design implementation of an encryption procedure using the Karatsuba algorithm. Our hard- ware accelerator is 1.5 times faster than the state of the art for 1 encryption and 4 times faster for 4 encryptions.

Mots clés: Homomorphic encryption; Hardware/software co-design; CCS Concepts: • Security and privacy → Public key encryption; Hardware security implementation; • Hardware → Hardware accelerators; Homomorphic Encryption; Karatsuba; hardware accelerator; FV

Domaines: Cryptographie et sécurité [cs.CR]; Electronique; Traitement du signal et de l'image [eess.SP]

Vincent Migliore, Cédric Seguin, Maria Méndez Real, Vianney Lapotre, Arnaud Tisserand, et al.. A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm. ACM Transactions on Embedded Computing Systems (TECS), 2017, 16 (5s), ⟨10.1145/3126558⟩. ⟨hal-01630065⟩